Zero-copy Queues for Native Signal Processing Using the Virtual Memory System Gregory E. Allen, Paul E. Zucknick, and Brian L. Evans Applied Research Laboratories, and Dept. of Electrical and Computer Engineering The Uni

Source URL: users.ece.utexas.edu

• Digital signal processing
• Computer memory
• Computing
• Mathematical analysis
• Signal processing
• Fast Fourier transform
• Zero-copy
• Finite impulse response
• Queue
• Data buffer

Minimizing Stall Time in Single and Parallel Disk Systems Susanne Albers Naveen Garg y Abstract

Source URL: www14.in.tum.de

• Cache
• Computing
• Computer memory
• Computer architecture
• Computer engineering
• Mathematics
• Virtual memory
• Integral
• Locality of reference
• Interval
• Paging
• CPU cache

Paging in TinyOS Provide dynamic memory and paging capabilities in TinyOS using virtual addressing Robin Z¨

Source URL: disco.ethz.ch

• Computing
• Computer memory
• Memory management
• Computer hardware
• Computer architecture
• Non-volatile memory
• Virtual memory
• C dynamic memory allocation
• Flash memory
• Random-access memory
• Paging
• EEPROM

Adaptive Insertion Policies for High Performance Caching Moinuddin K. Qureshi† Aamer Jaleel§ Yale N. Patt† Simon C. Steely Jr.§ Joel Emer§ †ECE Department The University of Texas at Austin {moin,

Source URL: researcher.watson.ibm.com

• Virtual memory
• Cache
• Computing
• Software
• Computer architecture
• Cache algorithms
• CPU cache
• Adaptive replacement cache
• Thrashing
• Working set
• Paging
• Pseudo-LRU

CS264: Beyond Worst-Case Analysis Lecture #3: Online Paging and Resource Augmentation∗ Tim Roughgarden† September 29,

Source URL: theory.stanford.edu

• Online algorithms
• Applied mathematics
• Mathematics
• Cache
• Computer science
• Analysis of algorithms
• Virtual memory
• Sorting algorithms
• Cache algorithms
• Competitive analysis
• CPU cache
• Algorithm

E cient Software-Based Fault Isolation Robert Wahbe Steven Lucco Thomas E. Anderson

Source URL: www.cs.cmu.edu

• Computing
• Computer architecture
• Computer engineering
• Central processing unit
• Instruction set architectures
• Assembly languages
• Processor register
• MIPS instruction set
• Instruction set
• Addressing mode
• Virtual memory
• CPU cache

Accelerating Two-Dimensional Page Walks for Virtualized Systems Ravi Bhargava Computing Solutions Group Advanced Micro Devices Austin, TX

Source URL: vglab.cse.iitd.ac.in

• Computer hardware
• Computing
• Computer architecture
• Memory management
• Central processing unit
• Virtual memory
• Computer memory
• Hardware virtualization
• Translation lookaside buffer
• Page table
• Second Level Address Translation
• CPU cache

Reclamationist of the Year Award Criteria This award is intended for individuals demonstrating outstanding accomplishments in the practical application or evaluation of reclamation technology. The individual may work in

Source URL: www.asmr.us

• Memory management
• Paging
• Virtual memory

Product: May 2016 Data Product Description

Source URL: www.psma.com.au

• Computing
• Postal system
• Geocoding
• Virtual memory
• Data types
• Address
• Postal code
• Physical address
• Data

Pantone Logo no tagline-REG-white

Source URL: www.econolite.com